Mappy VM has 4 DMA (direct memory access) channels which can normally copy memory faster than the CPU alone can. DMA is not faster than the CPU when performing fills. Each channel has a source and destination address, count, and control register. The control register determines when the DMA transfer will occur, whether halfwords or words should be transferred, and how the addresses should be changed during the transfer. There is a lot of flexibility, but DMA is typically just used to copy blocks of data from one part of memory to another.
The four channels have slightly different limitations, and are intended for different uses. Since a DMA transfer can be initiated by other subsystems, there is a priority scheme in place for the transfers:
There is no possibility for the CPU to do other things during a transfer, although all other subsystems continues to operate. The only snag is that an immediate DMA transfer starts 2 cycles after the enable bit is set, not instantly, so do not start multiple transfers on the same channel using back to back writes to the CR. This is a rare situation, since seperate transfers would typically need writes to the address and count registers in between writes to the control register.
DMAx_SRC
)Offset | Name | Type | F | E | D | C | B | A | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
$0B0 | DMA0_SRC_L | Write Only | Low 16 of 27 bit source address | |||||||||||||||
$0B2 | DMA0_SRC_H | Write Only |   | High 11 of 27 bit source address | ||||||||||||||
$0BC | DMA1_SRC_L | Write Only | Low 16 of 28 bit source address | |||||||||||||||
$0BE | DMA1_SRC_H | Write Only |   | High 12 of 28 bit source address | ||||||||||||||
$0C8 | DMA2_SRC_L | Write Only | Low 16 of 28 bit source address | |||||||||||||||
$0CA | DMA2_SRC_H | Write Only |   | High 12 of 28 bit source address | ||||||||||||||
$0D4 | DMA2_SRC_L | Write Only | Low 16 of 28 bit source address | |||||||||||||||
$0D6 | DMA2_SRC_H | Write Only |   | High 12 of 28 bit source address |
DMAx_DEST
)Offset | Name | Type | F | E | D | C | B | A | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
$0B4 | DMA0_DEST_L | Write Only | Low 16 of 27 bit destination address | |||||||||||||||
$0B6 | DMA0_DEST_H | Write Only |   | High 11 of 27 bit destination address | ||||||||||||||
$0C0 | DMA1_DEST_L | Write Only | Low 16 of 27 bit destination address | |||||||||||||||
$0C2 | DMA1_DEST_H | Write Only |   | High 11 of 27 bit destination address | ||||||||||||||
$0CC | DMA2_DEST_L | Write Only | Low 16 of 27 bit destination address | |||||||||||||||
$0CE | DMA2_DEST_H | Write Only |   | High 11 of 27 bit destination address | ||||||||||||||
$0D8 | DMA3_DEST_L | Write Only | Low 16 of 28 bit destination address | |||||||||||||||
$0DA | DMA3_DEST_H | Write Only |   | High 12 of 28 bit destination address |
DMAx_SIZE
)Offset | Name | Type | F | E | D | C | B | A | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
$0B8 | DMA0_SIZE | Write Only |   | Transfer Count | ||||||||||||||
$0C4 | DMA1_SIZE | Write Only |   | Transfer Count | ||||||||||||||
$0D0 | DMA2_SIZE | Write Only |   | Transfer Count | ||||||||||||||
$0DC | DMA3_SIZE | Write Only | Transfer Count |
DMAx_CR
)Offset | Name | Type | F | E | D | C | B | A | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
$0BA | DMA0_CR | Read Write | Enabled | IRQ | Start Mode |   | Width | Repeat | Source Mode | Dest Mode |   | |||||||
$0C6 | DMA1_CR | Read Write | Enabled | IRQ | Start Mode |   | Width | Repeat | Source Mode | Dest Mode |   | |||||||
$0D2 | DMA2_CR | Read Write | Enabled | IRQ | Start Mode |   | Width | Repeat | Source Mode | Dest Mode |   | |||||||
$0DE | DMA3_CR | Read Write | Enabled | IRQ | Start Mode | Width | Repeat | Source Mode | Dest Mode |   |
DMA_DEST_INC
)DMA_DEST_DEC
)DMA_DEST_FIXED
)DMA_DEST_INCREMENT_RELOAD
)DMA_SRC_INC
)DMA_SRC_DEC
)DMA_SRC_FIXED
)DMA_REPEAT
.DMA_16BIT
and DMA_32BIT
.DMA_START_NOW
)DMA_START_VBL
)DMA_START_HBL
)DMA_START_FIFO
). For more information, see the SDK documents on sound.DMA_IRQ_ENABLE
.DMA_ENABLE
.
Example: Transferring something or other.
// fixme: write some code
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