Timer Subsystem

There are 4 16 bit timers, which count up according to either a specified frequency or via a cascade. When a timer overflows (crosses from FFFF to 0000), other timers can be incremented (if the cascade bit in the following timer is set), and an interrupt can occur, if the interrupt request bit is set.
Timers are useful for implementing the passage of time in a game, to profile code, or when producing sound.


Timer Control Registers (TIMERx_CR)

OffsetNameType FEDCBA98 76543210
$102 TIMER0_CR Read Write   Enabled Trigger IRQ   Cascade Mode Frequency
$106 TIMER1_CR Read Write   Enabled Trigger IRQ   Cascade Mode Frequency
$10A TIMER2_CR Read Write   Enabled Trigger IRQ   Cascade Mode Frequency
$10E TIMER3_CR Read Write   Enabled Trigger IRQ   Cascade Mode Frequency

Details


Timer Data Registers (TIMERx_DATA)

OffsetNameType FEDCBA98 76543210
$100 TIMER0_DATA Read Only Current timer value
$104 TIMER1_DATA Read Only Current timer value
$108 TIMER2_DATA Read Only Current timer value
$10C TIMER3_DATA Read Only Current timer value

OffsetNameType FEDCBA98 76543210
$100 TIMER0_DATA Write Only Timer latch value
$104 TIMER1_DATA Write Only Timer latch value
$108 TIMER2_DATA Write Only Timer latch value
$10C TIMER3_DATA Write Only Timer latch value

Details

Reading a timer data register returns the current value of the timer.

Any value written to a timer data register sets the latch for that timer. A write to a latch doesn't modify the value read from the register immediately, it is loaded into the timer whenever it overflows. For instance, writing FFFFh would result in the timer overflowing every time it counts up. The default value in the latches is 0000h.


Uses and examples

Example: timer usage.

// fixme: insert code here

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