Mappy VM has a number of different memory spaces, some of which are internal and fixed, while others vary in size and availability depending on the cartridge loaded.
Description | Base | Size | Access Width | Wait States | Mirrors |
System ROM | 0x00000000 |
0x4000 |
8/16/32 | none | |
Cannot be accessed by user code | |||||
External RAM | 0x02000000 |
0x40000 |
8/16/32 | +2N/+2S | Mirrored from 0x02000000 to 0x02FFFFFF |
This RAM is only external to the CPU, and is not actually on the cartridge | |||||
Work RAM | 0x03000000 |
0x8000 |
8/16/32 | none | Mirrored from 0x03000000 to 0x03FFFFFF |
This is the fastest RAM available, and is often used to store ARM code doing processor intensive tasks | |||||
I/O Register Space | 0x04000000 |
N/A | 8/16/32 | variable | fixme |
All system I/O is handled through these memory mapped registers | |||||
Palette RAM | 0x05000000 |
0x400 |
16/32 | none | Mirrored from 0x05000000 to 0x05FFFFFF |
Holds background and sprite palettes | |||||
Video RAM | 0x06000000 |
0x18000 |
16/32 | Accesses may stall durring display | covered |
Contains all graphics and maps | |||||
Sprite RAM (OAM) | 0x07000000 |
0x400 |
16/32 | Accesses will stall durring display | Mirrored from 0x07000000 to 0x07FFFFFF |
Contains all sprite attributes | |||||
Cartridge ROM | 0x08000000 |
0..32 MB | 8/16/32 | variable | Mirrored from 0x08000000 to 0x0DFFFFFF unless EEPROM is present
|
All user code is initially held here | |||||
Serial EEPROM | 0x0D000000 |
4, 64 Kbit | 8/16/32 | variable | EEPROM when present is wired to A23 and D0, so it is mirrored across the top 16 MB of each ROM window |
Some cartridges have either SRAM or flash ROM on board | |||||
Cartridge RAM | 0x0E000000 |
0..64 KB | 8 | variable | Mirrored from 0x0E000000 to 0x0FFFFFFF when present in a cartridge |
Some cartridges have either SRAM or flash ROM on board |
The system ROM contains a boot-up sequence, the exception vectors, and a number of system utilities collectivley called the BIOS (Basic Input/Output System).
The BIOS is banked out of memory when the PC is not within the BIOS itself, and so cannot be accessed by normal means. A BIOS function is executed using a SWI
call with arguments in r0-r3.
All memory contained on the cartridge has variable wait states controlled by the wait state register WS_CR. A wait state is an additional delay incurred durring a memory access because of the slower components used to save money. There are two types of memory access cycles, a N cycle, which is a non-sequential access and is typically longer than the other type, an S or sequential access. A sequential access is any one that follows the last memory access by 2 or 4 bytes. Both both N and S accesses cost one cycle from fast, internal memory. The wait states are listed as +N/+S and indicate the additional cycle penalty for each type of access. Thus a halfword read from external ram actually costs 3 cycles, not 1.
WS_CR
)Offset | Name | Type | F | E | D | C | B | A | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
$204 | WS_CR | Read Write | Cartridge Type (R) | Prefetch Enable |   | Cart Clock | Bank 2 | Bank 1 | Bank 0 | SRAM mode |
Copyright © 2001 to 2002, Bottled Light, Inc.