CPU

2.1 Register Configuration

The register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers.

2.1.1 General Registers

The 16 general registers (R0-R15) are shown in figure 2.1. General registers are used for data processing and address calculation. R0 is also used as an index register, and several instructions use R0 as a fixed source or destination register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15.

Figure 2.1 General Registers Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing.

2.1.2 Control Registers

The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR), and vector base register (VBR) (figure 2.2). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts).

Figure 2.2 Control Registers

2.1.3 System Registers

System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC) (figure 2.3). The multiply and accumulate registers store the results of multiply and accumulate operations. The procedure register stores the return address from the subroutine procedure. The program counter stores program addresses to control the flow of the processing.

Figure 2.3 System Registers

2.1.4 Initial Values of Registers

Table 2.1 lists the values of the registers after reset.

Table 2.1 Initial Values of Registers

2.2 Data Formats

2.2.1 Data Format in Registers

Register operands are always longwords (32 bits) (figure 2.4). When the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.

Figure 2.4 Longword Operand

2.2.2 Data Format in Memory

Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed (figure 2.5). The hardware stack area, referred to by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. See the SH 7032/34 Hardware User Manual for more information on address errors.

This microprocessor has a function that allows access of CSZ space (area 2) in little endian format, which enables the microprocessor to share memory with processors that access memory in little endian format. The microprocessor arranges byte data differently for little endian and the more usual big endian format.

Figure 2.5 Byte, Word, and Longword Alignment

2.2.3 Immediate Data Format

Byte immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register.

Word or longword immediate data is not located in the instruction code: it is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Specific examples are given in table 2.5, Immediate Data Accessing.

2.3 Instruction Features

2.3.1 RISC-Type Instruction Set

All instructions are RISC type. This section details their functions.

16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.

One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using the pipeline system. Instructions are executed in 35 ns at 28.7 MHz.

Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data (table 2.2). Immediate data is sign-extended for arithmetic operations or zero-extended for logic operations. It also is handled as longword data.

Table 2.2 Sign Extension of Word Data

Note: @(disp, PC) accesses the address of the immediate data.

Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory.

Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the instruction that follows the branch instruction, and then branching reduces pipeline disruption during branching (table 2.3).

Table 2.3 Delayed Branch Instructions

Multiplication/Accumulation Operation: 16-bit X 16-bit --> 32-bit multiplication operations are executed in one to two cycles. 16-bit X 16-bit + 64-bit --> 64-bit multiplication/accumulation operations are executed in two to three cycles. 32-bit X 32-bit --> 64-bit and 32-bit X 32-bit + 64­bit --> 64-bit multiplication/accumulation operations are executed in two to four cycles.

T Bit: The T bit in the status register changes according to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch (table 2.4). The number of instructions after the T bit in the status register is kept to a minimum to improve the processing speed.

Table 2.4 T Bit

Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate data is not input via instruction codes but is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement (table 2.5).

Table 2.5 Immediate Data Accessing

Note: @(disp, PC) accesses the address of the immediate data.

Absolute Address: When data is accessed by absolute address, the value already in the absolute address is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect register addressing mode (table 2.6).

Table 2.6 Absolute Address Accessing

Note: @(disp,PC) accesses the address of the immediate data.

16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the pre-existing displacement value is placed in the memory table. Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7).

Table 2.7 16/32-Bit Displacement Accessing

Note: @(disp,PC) accesses the address of the immediate data.

2.3.2 Addressing Modes

Table 2.8 describes addressing modes and effective address calculation.

Table 2.8 Addressing Modes and Effective Addresses

Table 2.8 Addressing Modes and Effective Addresses (cont)

Table 2.8 Addressing Modes and Effective Addresses (cont)

Table 2.8 Addressing Modes and Effective Addresses (cont)

2.3.3 Instruction Format

The instruction format table, table 2.9, refers to the source operand and the destination operand. The meaning of the operand depends on the instruction code. The symbols are used as follows:

• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement

Table 2.9 Instruction Formats

Table 2.9 Instruction Formats (cont)

Instruction Formats	Source Operand	Destination Operand	Example
nm format	mmmm: Direct register	nnnn: Indirect register	ADD Rm,Rn
	mmmm: Direct register	nnnn: Direct register	MOV.L Rm,@Rn
--	mmmm: Indirect post-increment register (multiply/ accumulate) nnnn: Indirect post-increment register (multiply/ accumulate)*	MACH, MACL	MAC.W @Rm+,@Rn+
--	mmmm: Indirect post-increment register	nnnn: Direct register	MOV.L @Rm+,Rn
--	mmmm: Direct register	nnnn: Indirect pre-decrement register	MOV.L Rm,@-Rn
--	mmmm: Direct register	nnnn: Indirect indexed register	MOV.L Rm,@(R0,Rn)
md format	mmmmdddd: indirect register with displacement	R0 (Direct register)	MOV.B @(disp,Rn),R0
nd4 format	R0 (Direct register)	nnnndddd: Indirect register with displacement	MOV.B R0,@(disp,Rn)
nmd format	mmmm: Direct register	nnnndddd: Indirect register with displacement	MOV.L Rm,@(disp,Rn)
--	mmmmdddd: Indirect register with displacement	nnnn: Direct register	MOV.L @(disp,Rm),Rn

Table 2.9 Instruction Formats (cont)

Instruction Formats	Source Operand	Destination Operand	Example
d format	dddddddd: Indirect GBR with displacement	R0 (Direct register)	MOV.L @(disp,GBR),R0
--	R0(Direct register)	dddddddd: Indirect GBR with displacement	MOV.L R0,@(disp,GBR)
--	dddddddd: PC relative with displacement	R0 (Direct register)	MOVA @(disp,PC),R0
--	dddddddd: PC relative	--	BF label
d12 format	dddddddddddd: PC relative	--	BRA label (label = disp + PC)
nd8 format	dddddddd: PC relative with displacement	nnnn: Direct register	MOV.L @(disp,PC),Rn
i format	iiiiiiii: Immediate	Indirect indexed GBR	AND.B #imm,@(R0,GBR)
	iiiiiiii: Immediate	R0 (Direct register)	AND #imm,R0
--	iiiiiiii: Immediate	--	TRAPA #imm
ni format	iiiiiiii: Immediate	nnnn: Direct register	ADD #imm,Rn

Note: In multiply/accumulate instructions, nnnn is the source register.

2.4 Instruction Set

2.4.1 Instruction Set by Classification

Table 2.10 Instruction Set by Classification

Table 2.10 Instruction Set by Classification (cont)

Table 2.10 Instruction Set by Classification (cont)

Table 2.11 shows the format for instruction codes, operation, and execution states used in tables 2.12 to 2.17, which list the minimum number of clock cycles required for execution. In practice, the number of execution cycles increases when the instruction fetch is in contention with data access or when the destination register of a load instruction (memory --> register) is the same as the register used by the next instruction.

Table 2.11 Instruction Code Format

1. Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. The actual number of cycles may be increased when:
2. Contention occurs between instruction fetch and data access
3. The destination register of the load instruction (memory --> register) and the register used by the next instruction are the same.
4. 2. Depending on the operand size, displacement is scaled X1, X2, or X3. For details, see the SH-1/SH-2 programming manual.

Table 2.12 Data Transfer Instructions

Table 2.12 Data Transfer Instructions (cont)

Table 2.13 Arithmetic Instructions

Table 2.13 Arithmetic Instructions (cont)

Table 2.13 Arithmetic Instructions (cont)

Note: The normal minimum number of execution cycles. (The number in parentheses is the number of cycles when there is contention with following instructions.)

Table 2.14 Logic Operation Instructions

Table 2.15 Shift Instructions

Table 2.16 Branch Instructions

Note: One state when it does not branch.

Table 2.17 lists the minimum execution cycles. In practice, the number of execution cycles increases when the instruction fetch is in contention with data access or when the destination register of a load instruction (memory --> register) is the same as the register used by the next instruction.

Table 2.17 System Control Instructions

Table 2.17 System Control Instructions (cont)

Note: The number of execution states before the chip enters the sleep mode.

Instruction states: The values shown for the execution cycles are minimums. The actual number of cycles may be increased when:

Contention occurs between instruction fetch and data access

The destination register of the load instruction (memory --> register) and the register used by the next instruction are the same.

2.4.2 Operation Code Map

Table 2.18 Operation Code Map

Table 2.18 Operation Code Map (cont)

Table 2.18 Operation Code Map (cont)

2.5 Processing States

2.5.1 State Transitions

The CPU has five processing states: reset, exception processing, bus release, program execution, and power-down. Figure 2.6 shows the transitions between the states. See section 14, Power-Down Mode, for more information on the power-down mode.

Figure 2.6 Transitions between Processing States

Reset State: The CPU resets in the reset state. This occurs when the \RES pin level goes low. When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will occur.

Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU's processing state flow.

For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins.

For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state.

Program Execution State: In the program execution state, the CPU sequentially executes the program.

Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the power-down state. This state has two modes: sleep mode and standby mode. See section 2.5.2 for more details.

Bus Release State: In the bus release state, the CPU releases access rights to the bus to the device that has requested them.

2.5.2 Power-Down State

Besides the ordinary program execution states, the CPU also has a power-down state in which CPU operation halts, lowering power consumption (table 2.19). There are two power-down state modes: sleep mode and standby mode.

Sleep Mode: When standby bit SBY (in the standby control register SBYCR) is cleared to 0 and a SLEEP instruction executed, the CPU moves from program execution state to sleep mode. The on-chip peripheral modules other than the CPU do not halt in the sleep mode. To return from sleep mode, use a reset, any interrupt, or a DMA address error; the CPU returns to the ordinary program execution state through the exception processing state.

Software Standby Mode: To enter the standby mode, set the standby bit SBY (in the standby control register SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip peripheral module, and oscillator functions are halted. However, when entering the standby mode, confirm that the DMAC master enable bit is 0. If a multiplication instruction is in process at a standby, the MACL and MACH registers will be invalid. CPU internal register contents and on-chip RAM data are held. Cache (and on-chip RAM) data is not held.

To return from standby mode, use a reset or an external NMI interrupt. For resets, the CPU returns to ordinary program execution state through the exception processing state when placed in a reset state after the oscillator stabilization time has elapsed. For NMI interrupts, the CPU returns to ordinary program execution state through the exception processing state after the oscillator stabilization time has elapsed. Turn the cache off before entering standby. In this mode, power consumption drops substantially because the oscillator stops.

Module Standby Function: The module standby function is available for the multiplier (MULT), divider (DIVU), 16-bit free-running timer (FRT), serial communications interface (SCI), and the DMA controller (DMAC) for the on-chip peripheral modules.

The supply of the clock to these on-chip peripheral modules can be halted by setting the corresponding bits 4-0 (MSTP4-MSTP0) in the standby control register (SBYCR). By using this function, the power consumption can be reduced.

The external pins of the on-chip peripheral modules in module standby are reset and all registers except DMAC, MULT, and DIVU are initialized. (The master enable bit (bit 0) of the DMAC's DMAOR register is initialized to 0). Module standby function is cleared by clearing the MSTP4-MSTP0 bits to 0.

When MULT has entered the software standby mode, do not execute the DMULS.L, DMULU.L, MAC.L, MAC.W, MUL.L, MULS, and MULU instructions (all of which are multiplication instruction) or any instructions that access the MACH and MACL registers (CLRMAC, LDS MACH/MACL, STS MACH/MACL).

When module standby functions of DMAC are used, set the DMA master enable bit in the DMAC to 0.

Table 2.19 Power-Down State

1. Notes: 1. Differs depending on peripheral module and pin.
2. 2. The DMAC, MULT, DIV registers and the specified interrupt vectors maintain their settings.